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| 208032-01 may 2009 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) 32, 64, and 128 mbit datasheet product features ? architecture ? symmetrical 128-kb blocks ? 128 mbit (128 blocks) ? 64 mbit (64 blocks) ? 32 mbit (32 blocks) ? performance ? 75 ns initial access speed ? 25 ns 8-word asynchronous page-mode reads ? 256-word write buffer for x16 mode, 256- byte write buffer for x8 mode; 4 s per byte effective programming time ? system voltage ?v cc = 2.7 v to 3.6 v ?v ccq = 2.7 v to 3.6 v ? packaging ?56-lead tsop ?64-ball numonyx ? easy bga package ? security ? enhanced security options for code protection ? 128-bit protection register: 64 unique device identification bits 64 user-programmable otp bits ? absolute protection with v pen = vss ? individual block locking ? block erase/program lockout during power transitions ? software ? program and erase suspend support ? flash data integrator (fdi), common flash interface (cfi) compatible ? scalable command set ? quality and reliability ? operating temperature: -40 c to +85 c ? 100k minimum erase cycles per block ? 65 nm etox? x flash technology
datasheet may 2009 2 208032-01 legal lines and disclaimers information in this document is provided in connection with numo nyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical co ntrol or safety systems, or in nuclear f acility applications. numonyx b.v. may make changes to specifications an d product descriptions at any time, without notice. numonyx b.v. may have patents or pending patent applications, tr ademarks, copyrights, or other intellectual property rights tha t relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implie d, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no respon sibility whatsoever for conf licts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to ob tain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting the numonyx website at http://www.numonyx.com . numonyx, the numonyx logo, and strataflash are trademarks or regist ered trademarks of numonyx b.v. or its subsidiaries in other countries. *other names and brands may be claimed as the property of others. copyright ? 2009, numonyx b.v., all rights reserved. may 2009 datasheet 208032-01 3 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) contents 1.0 introduction .............................................................................................................. 6 1.1 nomenclature ..................................................................................................... 6 1.2 acronyms........................................................................................................... 7 1.3 conventions ....................................................................................................... 7 2.0 functional overview .................................................................................................. 9 2.1 block diagram .................................................................................................. 11 2.2 memory map..................................................................................................... 12 3.0 package information ............................................................................................... 13 3.1 56-lead tsop package for 32-, 64-, 128-mbit ....................................................... 13 3.2 64-ball numonyx? easy bga package for 32-, 64-, 128-mbit.................................. 14 4.0 ballouts/pinouts and signal descriptions ................................................................ 16 4.1 numonyx? easy bga ballout for 32-, 64-, 128-mbit .............................................. 16 4.2 56-lead tsop package pinout for 32-, 64-,128-mbit .............................................. 17 4.3 signal descriptions ............................................................................................ 18 5.0 maximum ratings and operating conditions ............................................................ 19 5.1 absolute maximum ratings................................................................................. 19 5.2 operating conditions ......................................................................................... 19 5.3 power-up/down ................................................................................................ 19 5.3.1 power-up/down sequence....................................................................... 19 5.3.2 power supply decoupling ........................................................................ 20 5.4 reset............................................................................................................... 20 6.0 electrical characteristics ......................................................................................... 21 6.1 dc current specifications ................................................................................... 21 6.2 dc voltage specifications.................................................................................... 22 6.3 capacitance...................................................................................................... 22 7.0 ac characteristics ................................................................................................... 23 7.1 read specifications............................................................................................ 23 7.2 program, erase, block-lock specifications ........ .................................................... 28 7.3 reset specifications........................................................................................... 28 7.4 ac test conditions ............................................................................................ 29 8.0 bus interface ........................................................................................................... 30 8.1 bus reads ........................................................................................................ 31 8.1.1 asynchronous page mode read ................................................................ 31 8.1.2 output disable ....................................................................................... 32 8.2 bus writes........................................................................................................ 32 8.3 standby ........................................................................................................... 33 8.3.1 reset/power-down ................................................................................. 33 8.4 device commands............................................................................................. 33 9.0 flash operations ..................................................................................................... 34 9.1 status register ................................................................................................. 34 9.1.1 clearing the status register .................................................................... 35 9.2 read operations ............................................................................................... 35 9.2.1 read array ............................................................................................ 35 9.2.2 read status register .............................................................................. 36 9.2.3 read device information ......................................................................... 36 9.2.4 cfi query ............................................................................................. 36 9.3 programming operations.................................................................................... 36 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 4 208032-01 9.3.1 single-word/byte programming................................................................36 9.3.2 buffered programming ............................................................................37 9.4 block erase operations .......................................................................................38 9.5 suspend and resume .........................................................................................39 9.6 status signal ....................................................................................................40 9.7 security and protection.......................................................................................41 9.7.1 normal block locking ..............................................................................41 9.7.2 configurable block locking.......................................................................42 9.7.3 password access.....................................................................................42 9.7.4 128-bit protection register.......................................................................42 9.7.5 reading the 128-bit protection register .....................................................42 9.7.6 programming the 128-bit protection regist er..............................................42 9.7.7 locking the 128-bit protection register.... ..................................................43 9.7.8 vpen protection......................................................................................44 10.0 id codes ..................................................................................................................46 11.0 device command codes ...........................................................................................47 12.0 flow charts ..............................................................................................................48 13.0 common flash interface ..........................................................................................57 13.1 query structure output ......................................................................................57 13.2 query structure overview...................................................................................58 13.3 block status register .........................................................................................59 13.4 cfi query identification string ..................... .......................................................59 13.5 system interface information..............................................................................60 13.6 device geometry definition .................................................................................60 13.7 primary-vendor specific extended query table ......................................................61 a additional information .............................................................................................64 b ordering information ...............................................................................................65 may 2009 datasheet 208032-01 5 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) revision history date revision description may 2009 01 initial release numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 6 208032-01 1.0 introduction this document contains information pertaining to the numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) device features, operation, and specifications. unless otherwise indicated throughout the rest of this document, the numonyx? embedded flash memory (j3 65 nm) single bi t per cell (sbc) device is referred to as j3 65 nm sbc. the j3 65 nm sbc device provides improv ed mainstream performance with enhanced security features, taking advantage of the high quality and reliability of the nor-based 65 nm technology. offered in 128-mbit, 64-m bit, and 32-mbit densities, the j3 65 nm sbc device brings reliable, low-voltage capability (3 v read, program, and erase) with high speed, low-power operation. the j3 65 nm sbc device takes advantage of proven manufacturing experience and is ideal for code and data applications where high density and low cost are required, such as in networking, telecommunications, digital set top boxes, audio recording, and di gital imaging. numonyx flash memory components also deliver a new generation of forward-compatible software support. by using the common flash interface (cfi) and scalable command set (scs), customers can take advantage of density upgrades an d optimized write capabilities of future numonyx flash memory devices. 1.1 nomenclature j3 65 nm sbc numonyx? embedded flash memory (j 3 65 nm) single bit per cell (sbc) amin all densities amin = a0 for x8 all densities amin = a1 for x16 amax 32 mbit amax = a21 64 mbit amax = a22 128 mbit amax = a23 block a group of flash cells that share common erase circuitry and erase simultaneously. clear indicates a logic zero (0) program writes data to the flash array set indicates a logic one (1) vpen refers to a signal or package connection name v pen refers to timing or voltage levels may 2009 datasheet 208032-01 7 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) 1.2 acronyms 1.3 conventions h hexadecimal suffix k(noun) 1,000 m (noun) 1,000,000 nibble 4 bits byte 8 bits word 16 bits kb 1,024 bits kb 1,024 bytes kw 1,024 words mb 1,048,576 bits mb 1,048,576 bytes mw 1,048,576 words kbit 1,024 bits mbit 1,048,576 bits sbc single bit per cell fdi flash data integrator cfi common flash interface scs scalable command set cui command user interface otp one time programmable plr protection lock register pr protection register prd protection register data rfu reserved for future use sr status register srd status register data wsm write state machine ecr enhanced configuration register ecd enhanced configuration register data numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 8 208032-01 brackets square brackets ([]) will be used to designate group membership or to define a group of signals with sim ilar function (i.e. a[21:1], sr[4,1] and d[15:0]). 00ffh denotes 16-bit hexadecimal numbers 00ff 00ffh denotes 32-bit hexadecimal numbers dq[15:0] data i/o signals may 2009 datasheet 208032-01 9 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) 2.0 functional overview the j3 65 nm sbc family contains high-density memory organized in any of the following configurations: ? 16-mb or 8-mw (128-mbit), organized as one-hundred-twenty-eight 128-kb erase blocks. ? 8-mb or 4-mw (64-mbit), organized as sixty-four 128-kb erase blocks. ? 4-mb or 2-mw (32-mbit), organized as thirty-two 128-kb erase blocks. these devices can be accessed as 8- or 16-bit words. see figure 1, ?memory block diagram for 32-, 64-, 128-mbit? on page 11 for further details. a 128-bit protection register has multiple uses, including unique flash device identification. the j3 65 nm sbc device includes new security features that were not available on the (previous) 0.13m versions of the j3 fa mily. these new security features prevent altering of code through different protection schemes that can be implemented, based on user requirements. the j3 65 nm sbc optimized architecture an d interface dramatically increases read performance by supporting page-mode reads. this read mode is ideal for non-clock memory systems. its common flash interface (cfi) permits soft ware algorithms to be used for entire families of devices. this allows device -independent, jedec id-independent, and forward- and backward-compatible software support for the specified flash device families. flash vendors can standardize th eir existing interfaces for long-term compatibility. the scalable command set (scs) allows a sing le, simple software driver in all host systems to work with all scs-compliant flas h memory devices, independent of system- level packaging (e.g., memory card, simm, or direct-to-board placement). additionally, scs provides the highest syst em/device data transfer rates and minimizes device and system-level implementation costs. a command user interface (cui) serves as the interface between the system processor and internal operation of the device. a valid command sequence written to the cui initiates device automation . an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. a block erase operation erases one of the device?s 128-kb blocks typically within one second, independent of other blocks. each block can be independently erased 100,000 times. block erase suspend mode allows system software to suspend block erase to read or program data from any other block. similarly, program suspend allows system software to suspend programming (byte/word program and write-to-buffer operations) to read data or execute code from any other block that is not being suspended. each device incorporates a write buffer of 256-byte (x8 mode) or 256-word (x16 mode) to allow optimum programming performa nce. by using the write buffer data is programmed more efficiently in buffer increments. memory blocks are selectively and individua lly lockable in-system. individual block locking uses block lock-bits to lock and unlock blocks. block lock-bits gate block erase and program operations. lock-bit configuratio n operations set and clear lock-bits (using the set block lock-bit and clear block lock-bits commands). numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 10 208032-01 the status register indicates when the wsm?s block erase, program, or lock-bit configuration operation completes. the sts (status) output gives an additional indicator of wsm activity by providing both a hardware signal of status (versus softwa re polling) and status masking (interrupt masking for background block erase, for example). status indication using sts minimizes both cpu overhead and system power consumption. when configured in level mode (default mode), it acts as a ry/b y# signal. when low, sts indicates that the wsm is performing a block erase, program, or lock-bit configuration. sts-high indicates that the wsm is ready for a new command, block erase is suspended (and programming is inactive), prog ram is suspended, or the device is in reset/power-down mode. additionally, the configuration command allows the sts signal to be configured to pulse on completion of programming and/or block erases. three ce signals are used to enable and disable the device. a unique ce logic design (see table 17, ?chip enable truth table for 32-, 64-, 128-mb? on page 30 ) reduces decoder logic typically required for multi-chip designs. external logic is not required when designing a single chip, a dual chip, or a 4-chip miniature card or simm module. the byte# signal allows either x8 or x16 read/writes to the device: ? byte#-low enables 8-bit mode; address a0 selects between the low byte and high byte. ? byte#-high enables16-bit operation; address a1 becomes the lowest order address and address a0 is not used (don?t care). figure 1, ?memory block diagram for 32-, 64-, 128-mbit? on page 11 shows a device block diagram. when the device is disabled (see table 17, ?chip enable truth table for 32-, 64-, 128- mb? on page 30 ), with cex at v ih and rp# at v ih , the standby mode is enabled. when rp# is at v il , a further power-down mode is enabled which minimizes power consumption and provides write protection during reset. a reset time (t phqv ) is required from rp# going high until data ou tputs are valid. likewise, the device has a wake time (t phwl ) from rp#-high until writes to the cui are recognized. with rp# at v il , the wsm is reset and the status register is cleared. may 2009 datasheet 208032-01 11 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) 2.1 block diagram figure 1: memory block diagram for 32-, 64-, 128-mbit numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 12 208032-01 2.2 memory map figure 2: j3 65 nm sbc memory map byte-wide (x 8 ) mode 128 kb block 128 kb block 0 1 - - 128 kb block 31 - 128 kb block 63 - 128 kb block 127 - 32- mbit 64- mbit 128- mbit a [23:0]:128 mbit a [22:0]: 64mbit a [21:0]: 32mbit word-wide (x16) mode 64 kw block 64 kw block 0 1 - - 64 kw block 31 - 64 kw block 63 - 64 kw block 127 - 32- mbit 64- mbit 128- mbit a [23:1]:128 mbit a [22:1]: 64mbit a [21:1]: 32mbit f 0 f 0 f 0 0 e f f f fh h f f f f f 7h 0 0 0 0 e 7h f f f f f 3h 0 0 0 0 e 3h f f f f 3 0h 0 0 0 0 2 0h f f f f 1 0h 0 0 0 0 0 0h f 0 f 0 f 0 0 f 7 f f 7h h f f f f f 3h 0 0 0 0 f 3h f f f f f 1h 0 0 0 0 f 1h f f f f 1 0h 0 0 0 0 1 0h f f f f 0 0h 0 0 0 0 0 0h may 2009 datasheet 208032-01 13 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) 3.0 package information 3.1 56-lead tsop package for 32-, 64-, 128-mbit notes: 1. one dimple on package denotes pin 1. 2. if two dimples, then the larger dimple denotes pin 1. 3. pin 1 will always be in the upper left corner of the package, in refere nce to the product mark. figure 3: 56-lead tsop package mechanical a 0 l detail a y d c z pin 1 e d 1 b detail b see detail a e see detail b a 1 seating plane a 2 see note 2 see notes 1 and 3 table 1: 56-lead tsop dimension table parameter symbol millimeters inches min nom max min nom max package height a ? ? 1.200 ? ? 0.047 standoff a 1 0.050 ? ? 0.002 ? ? package body thickness a 2 0.965 0.995 1.025 0.038 0.039 0.040 lead width b 0.100 0. 150 0.200 0.004 0.006 0.008 lead thickness c 0.100 0.150 0.200 0.004 0.006 0.008 package body length d 1 18.200 18.400 18.600 0.717 0.724 0.732 package body width e 13.800 14.000 14.200 0.543 0.551 0.559 lead pitch e ? 0.500 ? ? 0.0197 ? terminal dimension d 19. 800 20.00 20.200 0.780 0.787 0.795 lead tip length l 0.500 0.600 0.700 0.020 0.024 0.028 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 14 208032-01 3.2 64-ball numonyx? easy bg a package for 32-, 64-, 128- mbit lead count n ? 56 ? ? 56 ? lead tip angle 0 3 5 0 3 5 seating plane coplanarity y ? ? 0.100 ? ? 0.004 lead to package offset z 0.150 0.250 0.350 0.006 0.010 0.014 table 1: 56-lead tsop dimension table parameter symbol millimeters inches min nom max min nom max figure 4: 64-ball numonyx? easy bga mechanical specifications 2 ball a1 corner 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 e a b c d e f g h seating plane s 1 s e b top view - plastic backside complete ink mark not shown bottom view - ball side up y a a1 d a b c d e f g h ball a1 corner a2 table 2: easy bga package dimensions table (sheet 1 of 2) parameter symbol millimeters inches min nom max min nom max package height a ? ? 1.200 ? ? 0.0472 ball height a1 0.250 ? ? 0.0098 ? ? package body thickness a2 ? 0.780 ? ? 0.0307 ? ball (lead) width b 0.310 0.410 0.510 0.012 0.016 0.020 may 2009 datasheet 208032-01 15 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) package body width d 9.900 10.000 10.100 0.3898 0.3937 0.3976 package body length e 12. 900 13.000 13.100 0.5079 0.5118 0.5157 pitch e ? 1.000 ? ? 0.0394 ? ball (lead) count n ? 64 ? ? 64 ? seating plane coplanarity y ? ? 0.100 ? ? 0.0039 corner to ball a1 distance along d s1 1.400 1.500 1.600 0.0551 0.0591 0.0630 corner to ball a1 distance along e s2 2.900 3.000 3.100 0.1142 0.1181 0.1220 table 2: easy bga package dime nsions table (sheet 2 of 2) parameter symbol millimeters inches min nom max min nom max numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 16 208032-01 4.0 ballouts/pinouts and signal descriptions j3 65 nm sbc is available in two package types. all densities of the j3 65 nm sbc devices are supported on both 64-ball numonyx? easy bga and 56-lead thin small outline package (tsop) packages. the figures below show the ballouts/pinouts. 4.1 numonyx? easy bga ballout for 32-, 64-, 128-mbit notes: 1. a0 is the least significant address bit. 2. a22 is valid on 64-mbit densities and abov e, otherwise, it is a no connect (nc). 3. a23 is valid on 128-mbit; otherwise, it is a no connect (nc). 4. a24 is a no connect (nc) on 128-, 64-, 32- mbit, and reserved for 256-mbit. figure 5: numonyx? easy bg a ballout (32/64/128 mbit) a1 a6 a8 vpen a13 vcc a18 a22 a2 vss a9 ce0 a14 rfu a19 ce1 a3 a7 a10 a12 a15 rfu a20 a21 a4 a5 a11 rp# rfu rfu a16 a17 dq8 dq1 dq9 dq3 dq4 rfu dq15 sts byte# dq0 dq10 dq11 dq12 rfu rfu oe# a23 a0 dq2 vccq dq5 dq6 dq14 we# ce2 rfu vcc vss dq13 vss dq7 a24 12345678 a b c d e f g h easy bga top view ? ball side down a22 ce1 a21 a17 sts oe # we# a24 8 a18 a19 a20 a16 dq15 rfu dq14 dq7 7 vcc rfu rfu rfu rfu rfu dq6 vss 6 a13 a14 a15 rfu dq4 dq12 dq5 dq13 5 vpen ce0 a12 rp# dq3 dq11 vccq vss 4 a8 a9 a10 a11 dq9 dq10 dq2 vcc 3 a6 vss a7 a5 dq1 dq0 a0 rfu 2 a1 a2 a3 a4 dq8 byte# a23 ce2 1 a b c d e f g h easy bga bottom view ? ball side up (1 ) (3) (4) (2) (2 ) (4 ) (3) (1) may 2009 datasheet 208032-01 17 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) 4.2 56-lead tsop package pi nout for 32-, 64-,128-mbit notes: 1. no internal connection for pin 9; it may be driven or floated. for legacy designs, the pin can be tied to v cc . 2. a0 is the least significant address bit. 3. a22 exists on 64- and 128- densities. on 32-mbit density this signal is a no-connect (nc). 4. a23 exists on 128-mbit densities. on 32- and 64-mbit densities this signal is a no-connect (nc). 5. a24 is a no connect (nc) on 128-, 64-, 32- mbit, reserved for 256-mbit. figure 6: 56-lead tsop package pinout (32/64/128 mbit) 56-lead tsop package 14 mm x 20 mm top view a 22 ce1 a 21 a 19 a 18 a 17 a 16 vcc a 15 a 14 a 13 a 12 ce0 vpen rp# a 11 a 10 a 9 a 8 vss a 7 a 6 a 5 a 4 a 3 a 2 a 20 a 1 a 24 we# oe # dq 15 dq 7 dq 14 dq 6 vss dq 13 dq 5 dq 12 dq 4 vccq vss dq 11 dq 3 dq 10 dq 2 vcc dq 9 dq 1 dq 8 dq 0 a 0 byte# a 23 sts ce2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 (3) (5) (4) (2) (1 ) numonyx tm embedded flash memory j3 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 18 208032-01 4.3 signal descriptions ta b l e 3 lists the active signals used on j3 65 nm sbc and provides a description of each. table 3: signal descriptions for j3 65 nm sbc symbol type name and function a0 input byte-select address: selects between high and low byte when the device is in x8 mode. this address is latched during a x8 program cycle. not used in x16 mode (i.e., the a0 input buffer is turned off when byte# is high). a[max:1] input address inputs: inputs for addresses during read and program operations. addresses are internally latched during a program cycle: 32-mbit ? a[21:1] 64-mbit? a[22:1] 128-mbit ? a[23:1] dq[7:0] input/ output low-byte data bus: inputs data during buffer writes and programming, and inputs commands during cui writes. outputs array, cfi, identifier, or status data in the appropriate read mode. data is internally latched during write operations. dq[15:8] input/ output high-byte data bus: inputs data during x16 buffer writes and programming operations. outputs array, cfi, or identifier data in the appropriate read mode; not used for status register reads. data is internally latched during write op erations in x16 mode. d[15:8] float in x8 mode. ce[2:0] input chip enable: activates the 32-, 64-, 128-mbit devices? control logic, input buffers, decoders, and sense amplifiers. when the device is de-selected (see table 17, ?chip enable truth table for 32-, 64-, 128-mb? on page 30 ), power reduces to standby levels. all timing specifications are the same for these thre e signals. device selection occurs with the first edge of ce0, ce1, or ce2 that en ables the device. device deselection occurs with the first edge of ce0, ce1, or ce2 that disables the device (see table 17, ?chip enable truth table for 32-, 64-, 128-mb? on page 30 ). rp# input reset: rp#-low resets internal automation and puts the device in power-down mode. rp#-high enables normal operation. exit from reset sets th e device to read array mode. when driven low, rp# inhibits write operations which provides data protection during power transitions. oe# input output enable: activates the device?s outputs through the data buffers during a read cycle. oe# is active low. we# input write enable: controls writes to the cui, the write bu ffer, and array blocks. we# is active low. addresses and data are latched on the rising edge of we#. sts open drain output status: indicates the status of the internal stat e machine. when config ured in level mode (default), it acts as a ry/by# signal. when config ured in one of its pulse modes, it can pulse to indicate program and/or erase completion. for altern ate configurations of the status signal, see the configurations command and section 9.6, ?status signal? on page 40 . sts is to be tied to vccq with a pull-up resistor. byte# input byte enable: byte#-low places the device in x8 mode; data is input or output on d[7:0], while d[15:8] is placed in high-z. address a0 selects between the high and low byte. byte#-high places the device in x16 mode, and turns off the a0 inpu t buffer, the address a1 becomes the lowest-order address bit. vpen input erase / program / block lock enable: for erasing array blocks, programming data, or configuring lock-bits. with v pen v penlk , memory contents cannot be altered. vcc power core power supply: core (logic) source voltage. writes to the flash array are inhibited when v cc v lko . caution: device operation at invalid vcc voltages should not be attempted. vccq power i/o power supply: power supply for input/output buffers .this ball can be tied directly to v cc . vss supply ground: ground reference for device logic voltages. connect to system ground. nc ? no connect: lead is not interna lly connected; it may be driven or floated. rfu ? reserved for future use: balls designated as rfu are reserved by numonyx for future device functionality and enhancement . may 2009 datasheet 208032-01 19 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) 5.0 maximum ratings and operating conditions 5.1 absolute maximum ratings warning: stressing the device beyond the ?absolut e maximum ratings? may cause permanent damage. these are stress ratings only. 5.2 operating conditions warning: operations beyond the ?operating condit ions? is not recommended and extended exposure beyond the ?operating cond itions? may affect device reliability. 5.3 power-up/down this section provides an overview of system level considerations with regards to the flash device. it includes a brief description of power-up/down sequence and decoupling design considerations. 5.3.1 power-up/down sequence to prevent conditions that could result in spurious program or erase operations, the power-up/power-down sequence shown in ta b l e 6 is recommended. for dc voltage characteristics refer to ta b l e 8 . note that each power supply must reach its minimum voltage range before applying/rem oving the next supply voltage. notice: this document contains information available at the time of its release. the specificatio ns are subject to change witho ut notice. verify with your local numonyx sales office that you have the latest datasheet before finalizing a design. table 4: absolute maximum ratings parameter min max unit notes temperature under bias expanded (t a , ambient) ?40 +85 c ? storage temperature ?65 +125 c ? vcc voltage ?2.0 +5.6 v 2 vccq voltage ?2.0 +5.6 v 2 voltage on any input/output signal (except vcc, vccq) ?2.0 v ccq (max) + 2.0 v 1 i sh output short circuit current ? 100 ma 3 notes: 1. voltage is referenced to v ss . during infrequent non-periodic transitions, the voltage potential between v ss and input/ output pins may undershoot to ?2.0 v for periods < 20 ns or overshoot to v ccq (max) + 2.0 v for periods < 20 ns. 2. during infrequent non-periodic transitions, the voltage potential between v cc and the supplies may undershoot to ?2.0 v for periods < 20 ns or v supply (max) + 2.0 v for periods < 20 ns. 3. output shorted for less than one second. one output pin/ball shorted at a time table 5: temperature and v cc operating condition symbol parameter min max unit test condition t a operating temperature -40.0 +85 c ambient temperature v cc vcc supply voltage 2.70 3.6 v ? v ccq vccq supply voltage 2.70 3.6 v ? numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 20 208032-01 note: 1. power supplies connected or sequenced together. device inputs must not be driven until all supply voltages reach their minimum range. rp# should be low during power transitions. 5.3.2 power supply decoupling when the device is enabled, many internal conditions change. circ uits are energized, charge pumps are switched on, and internal voltage nodes are ramped. all of this internal activities produce transient signals. the magnitude of the transient signals depends on the device and system loading. to minimize the effect of these transient signals, a 0.1 f ceramic capacitor is required across each vcc/vss and vccq signal. capacitors should be placed as close as possible to device connections. additionally, for every eight flash devices, a 4.7 f electrolytic capacitor should be placed between vcc and vss at the power su pply connection. this 4.7 f capacitor should help overcome voltage slumps caused by pcb trace inductance. 5.4 reset by holding the flash device in reset duri ng power-up and power-down transitions, invalid bus conditions may be masked. the fl ash device enters reset mode when rp# is driven low. in reset, internal flash circuitry is disabled and outputs are placed in a high- impedance state. after return from reset, a certain amount of time is required before the flash device is able to perform normal op erations. after return from reset, the flash device defaults to asynchronous page mode. if rp# is driven low during a program or erase operation, the program or erase op eration will be aborted and the memory contents at the aborted block or address are no longer valid. see figure 12, ?ac waveform for reset operation? on page 28 for detailed information regarding reset timings. table 6: power-up/down sequence power supply voltage power-up sequence power-down sequence v cc(min) 1st 1st 1st (1) sequencing not required (1) 3rd 2nd 2nd (1) sequencing not required (1) v ccq(min) 2nd 2nd (1) 2nd 1st (1) v pen(min) 3rd 2nd 1st 1st may 2009 datasheet 208032-01 21 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) 6.0 electrical characteristics 6.1 dc current specifications table 7: dc current characteristics v ccq 2.7 - 3.6v test conditions notes v cc 2.7 - 3.6v symbol parameter typ max unit i li input and v pen load current ? 1 a v cc = v cc max; v ccq = v ccq max v in = v ccq or v ss 1 i lo output leakage current ? 10 a v cc = v cc max; v ccq = v ccq max v in = v ccq or v ss 1 i ccs v cc standby current 50 120 a cmos inputs, v cc = v cc max; vccq = vccqmax device is disabled (see table 17, ?chip enable truth table for 32-, 64-, 128-mb? on page 30 ), rp# = v ccq 0.2 v 1,2,3 0.71 2 ma ttl inputs, v cc = v cc max, vccq = vccqmax device is disabled (see table 17, ?chip enable truth table for 32-, 64-, 128-mb? on page 30 ), rp# = v ih i ccd v cc power-down current 50 120 arp# = v ss 0.2 v, i out (sts) = 0 ma ? i ccr v cc page mode read current 8-word page 10 15 ma cmos inputs, v cc = v cc max, v ccq = v ccq max using standard 8 word page mode reads. device is enabled (see table 17, ?chip enable truth table for 32-, 64-, 128-mb? on page 30 ) f = 5 mhz, i out = 0 ma 1,3 30 54 ma cmos inputs,v cc = v cc max, v ccq = v ccq max using standard 8 word page mode reads. device is enabled (see table 17, ?chip enable truth table for 32-, 64-, 128-mb? on page 30 ) f = 33 mhz, i out = 0 ma i ccw v cc program or set lock-bit current 35 60 ma cmos inputs, v pen = v cc 1,4 40 70 ma ttl inputs, v pen = v cc i cce v cc block erase or clear block lock-bits current 35 70 ma cmos inputs, v pen = v cc 1,4 40 80 ma ttl inputs, v pen = v cc i ccws i cces v cc program suspend or block erase suspend current ?10ma device is enabled (see table 17, ?chip enable truth table for 32-, 64-, 128-mb? on page 30 ) 1,5 notes: 1. all currents are in rms unless otherwise noted. these currents are valid for all product versions (packages and speeds). contact numonyx or your local sales office for information about ty pical specifications. 2. includes sts. 3. cmos inputs are either v cc 0.2 v or v ss 0.2 v. ttl inputs are either v il or v ih . 4. sampled, not 100% tested. 5. i ccws and i cces are specified with the device selected. if the device is read or written while in erase suspend mode, the device?s current draw is i ccr and i ccws . numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 22 208032-01 6.2 dc voltage specifications 6.3 capacitance notes: 1. sampled, not 100% tested. 2. t a = -40 c to +85 c, v cc = v ccq = 0 to 3.6 v. table 8: dc voltage characteristics v ccq 2.7 - 3.6 v test conditions notes v cc 2.7 - 3.6 v symbol parameter min max unit v il input low voltage ?0.5 0.8 v ? 2, 5, 6 v ih input high voltage 2.0 v ccq + 0.5 v ? 2, 5, 6 v ol output low voltage ?0.4v v cc = v cc min v ccq = v ccq min i ol = 2 ma 1, 2 ?0.2v v cc = v cc min v ccq = v ccq min i ol = 100 a v oh output high voltage 0.85 v ccq ?v v cc = v ccmin v ccq = v ccq min i oh = ?2.5 ma 1, 2 v ccq ? 0.2 ? v v cc = v ccmin v ccq = v ccq min i oh = ?100 a v penlk v pen lockout during program, erase and lock-bit operations ?2.2v?2, 3 v penh v pen during block erase, program, or lock-bit operations 2.7 3.6 v ? 3 v lko v cc lockout voltage ? 2.0 v ? 4 notes: 1. includes sts. 2. sampled, not 100% tested. 3. block erases, programming, and lock-bit configurations are inhibited when v pen v penlk , and not guaranteed in the range between v penlk (max) and v penh (min), and above v penh (max). 4. block erases, programming, and lock-bit configurations are inhibited when v cc < v lko , and not guaranteed in the range between v lko (min) and v cc (min), and above v cc (max). 5. includes all operational modes of the device. 6. input/output signals can undershoot to -1.0v referenced to v ss and can overshoot to v ccq + 1.0v for duration of 2ns or less, the v ccq valid range is referenced to v ss . table 9: capacitance symbol parameter 1 type max unit condition 2 c in input capacitance 67pf v in = 0.0 v c out output capacitance 45pf v out = 0.0 v may 2009 datasheet 208032-01 23 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) 7.0 ac characteristics timing symbols used in the timing diagrams within this document conform to the following convention. note: exceptions to this convention include t acc and t apa . t acc is a generic timing symbol that refers to the aggregate initial-access delay as determined by t avqv , t elqv , and t glqv (whichever is satisfied last) of the flash device. t apa is specified in the flash device?s data sheet, and is the address-to-data delay for subsequent page-mode reads. 7.1 read specifications figure 7: timing signal naming convention table 10: timing signal name decoder signal code state code address a high h data - read q low l data - write d high-z z chip enable (ce) e low-z x output enable (oe#) g valid v write enable (we#) w invalid i status (sts) r reset (rp#) p byte enable (byte#) f erase/program/block lock enable (v pen ) v table 11: read operations (sheet 1 of 2) asynchronous specifications v cc = 2.7 v?3.6 v (3) and v ccq = 2.7 v?3.6 v (3) # sym parameter density min max unit notes r1 t avav read/write cycle time 32 mbit 75 ? ns 1,2 64 mbit 75 ? 1,2 128 mbit 75 ? 1,2 e t l q v source signal target state source state target signal numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 24 208032-01 notes: 1. ce x low is defined as the combination of pins ce0, ce1 and ce2 that enable the device. ce x high is defined as the combination of pins ce0, ce1, and ce2 that disable the device (see table 17, ?chip enable truth table for 32- , 64-, 128-mb? on page 30 ). 2. see ac input/output reference waveforms for the maximum allowable input slew rate. 3. oe# may be delayed up to t elqv -t glqv after the falling edge of ce x (see note 1 and table 17, ?chip enable truth table for 32-, 64-, 128-mb? on page 30 ) without impact on t elqv . 4. see figure 13, ?ac input/output reference waveform? on page 29 and figure 14, ?transient equivalent testing load circuit? on page 29 for testing characteristics. 5. sampled, not 100% tested. 6. for devices configured to standard word/byte read mode, r15 (t apa ) will equal r2 (t avqv ). r2 t avqv address to output delay 32 mbit ? 75 ns 1,2 64 mbit ? 75 1,2 128 mbit ? 75 1,2 r3 t elqv ce x to output delay 32 mbit ? 75 ns 1,2 64 mbit ? 75 1,2 128 mbit ? 75 1,2 r4 t glqv oe# to non-array output delay all ? 25 ns 1,2,4 r5 t phqv rp# high to output delay 32 mbit ? 150 ns 1,2 64 mbit ? 180 1,2 128 mbit ? 210 1,2 r6 t elqx ce x to output in low z all 0 ? ns 1,2,5 r7 t glqx oe# to output in low z 0 ? ns 1,2,5 r8 t ehqz ce x high to output in high z ? 25 ns 1,2,5 r9 t ghqz oe# high to output in high z ? 15 ns 1,2,5 r10 t oh output hold from address, ce x , or oe# change, whichever occurs first 0 ? ns 1,2,5 r11 t elfl/ t elfh ce x low to byte# high or low ? 10 ns 1,2,5 r12 t flqv/ t fhqv byte# to output delay ? 1 s 1,2 r13 t flqz byte# to output in high z ? 1 s 1,2,5 r14 t ehel cex high to cex low 0 ? ns 1,2,5 r15 t apa page address access time ? 25 ns 5, 6 r16 t glqv oe# to array output delay ? 25 ns 1,2,4 table 11: read operations (sheet 2 of 2) asynchronous specifications v cc = 2.7 v?3.6 v (3) and v ccq = 2.7 v?3.6 v (3) # sym parameter density min max unit notes may 2009 datasheet 208032-01 25 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) notes: 1. ce x low is defined as the combination of pins ce0, ce1, and ce2 that enable the device. ce x high is defined as the combination of pins ce0, ce1, and ce2 that disable the device (see table 17, ?chip enable truth table for 32- , 64-, 128-mb? on page 30 ). 2. when reading the flash array a faster t glqv (r16) applies. for non-array reads, r4 applies (i.e., status register reads, query reads, or device identifier reads). notes: 1. ce x low is defined as the combination of pins ce0, ce1, and ce2 that enable the device. ce x high is defined as the combination of pins ce0, ce1, and ce2 that disable the device (see table 17, ?chip enable truth table for 32- , 64-, 128-mb? on page 30 ). 2. in this diagram, byte# is asserted high. figure 8: single-word asyn chronous read waveform address [a] r2 r1 r3 r 4 r7 r6 r5 cex [e] oe # [g] we# [w] dq[15:0] [q] byte# [f] rp# [p] r11 r12 r8 r9 r10 r13 figure 9: 8-word asynchronous page mode read a[max:4] [a] 000 111 1 2 8 7 r2 r1 r3 r4 r7 r6 r5 r10 r15 r10 r9 r8 a[3:1] [a] cex [e] oe # [g] we# [w] dq[15:0] [q] rp# [p] byte # [f] 001 110 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 26 208032-01 table 12: write operations #symbol parameter density valid for all speeds unit notes min max w1 t phwl (t phel ) rp# high recovery to we# (ce x ) going low 32 mbit 150 ? ns 1,2,3,4 64 mbit 180 ? 128 mbit 210 ? w2 t elwl (t wlel )ce x (we#) low to we# (ce x ) going low all 0 ? 1,2,3,5 w3 t wp write pulse width 60 ? 1,2,3,5 w4 t dvwh (t dveh ) data setup to we# (ce x ) going high 50 ? 1,2,3,6 w5 t avwh (t aveh )address setup to we# (ce x ) going high 55 ? 1,2,3,6 w6 t wheh (t ehwh )ce x (we#) hold from we# (ce x ) high 0 ? 1,2,3 w7 t whdx (t ehdx ) data hold from we# (ce x ) high 0 ? 1,2,3 w8 t whax (t ehax ) address hold from we# (ce x ) high 0 ? 1,2,3 w9 t wph write pulse width high 30 ? 1,2,3,7 w11 t vpwh (t vpeh )v pen setup to we# (ce x ) going high 0 ? 1,2,3,4 w12 t whgl (t ehgl ) write recovery before read 35 ? 1,2,3,8 w13 t whrl (t ehrl )we# (ce x ) high to sts going low ? 500 1,2,3,9 w15 t qvvl v pen hold from valid srd, sts going high 0 ? 1,2,3,4, 9,10 notes: 1. ce x low is defined as the combination of pins ce0, ce1, and ce2 that enable the device. ce x high is defined as the combination of pins ce0, ce1, and ce2 that disable the device (see table 17, ?chip enable truth table for 32-, 64-, 128-mb? on page 30 ). 2. read timing characteristics during block erase, program, an d lock-bit configuration operations are the same as during read-only operations. refer to ac characteristics?read-only operations . 3. a write operation can be initiate d and terminated with either ce x or we#. 4. sampled, not 100% tested. 5. write pulse width (t wp ) is defined from ce x or we# going low (whichever goes low last) to ce x or we# going high (whichever goes high first). hence, t wp = t wlwh = t eleh = t wleh = t elwh . 6. refer to table 18, ?enhanced configuration register? on page 32 for valid a in and d in for block erase, program, or lock-bit configuration. 7. write pulse width high (t wph ) is defined from ce x or we# going high (whichever goes high first) to ce x or we# going low (whichever goes low first). hence, t wph = t whwl = t ehel = t whel = t ehwl . 8. for array access, t avqv is required in addition to t whgl for any accesses after a write. 9. sts timings are based on sts configured in its ry/by# default mode. 10. v pen should be held at v penh until determination of block erase, program, or lock-bit configuration success (sr[5:3,1] = 0). may 2009 datasheet 208032-01 27 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) figure 10: asynchron ous write waveform address [a] d w8 w3 cex (we#) [e (w)] oe# [g] data [d/q] vpen [v] rp# [p] w2 w5 we# (cex) [w (e)] sts [r] w1 w6 w9 w4 w7 w13 w11 figure 11: asynchronous write to read waveform address [a] d w8 w3 cex [e] oe # [g] data [d/q] vpen [v ] rp# [p] w2 w5 we# [w] w1 w6 w12 w4 w7 w11 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 28 208032-01 7.2 program, erase, block-lock specifications 7.3 reset specifications note: sts is shown in its default mode (ry/by#). table 13: configuration performance # symbol parameter typ max (8) unit notes w16 t whqv7 t ehqv7 buffer program time aligned 16 words / 32 byte s 128 654 s 1,2,3,4,5,6,7 aligned 256 words tbd tbd us 1,2,3,4,5,6,7 w16 t whqv3 t ehqv3 block program time byte program time (using word/byte program command 40 175 s 1,2,3,4 aligned 16 words / 32 bytes 0.53 2.4 sec 1,2,3,4 aligned 256 words tbd tbd sec 1,2,3,4 w16 t whqv4 t ehqv4 block erase time 1.0 4.0 sec 1,2,3,4 w16 t whqv5 t ehqv5 set lock-bit time 50 60 s 1,2,3,4,9 w16 t whqv6 t ehqv6 clear block lock-bits time 0.5 0.70 sec 1,2,3,4,9 w16 t whrh1 t ehrh1 program suspend latency time to read 15 20 s 1,2,3,9 w16 t whrh t ehrh erase suspend latency time to read 15 20 s 1,2,3,9 w17 t sts sts pulse width low time 500 ? ns 1 notes: 1. typical values measured at t a = +25 c and nominal voltages. assumes correspond ing lock-bits are not se t. subject to change based on device characterization. 2. these performance numbers are valid for all speed versions. 3. sampled but not 100% tested. 4. excludes system-level overhead. 5. these values are valid when the buffer is full, and the start address is aligned. 6. effective per-byte program time (t whqv1 , t ehqv1 ) is 4s/byte (256-byte buffer, typical). 7. effective per-word program time (t whqv2 , t ehqv2 ) is 8s/word (256-word buffer, typical). 8. max values are measured at worst case temperature, data pattern and v cc corner after 100k cycles (except as noted). 9. max values are expressed at +25 c or -40 c. figure 12: ac waveform for reset operation p3 p1 p2 p1 sts (r) rp# (p) vcc may 2009 datasheet 208032-01 29 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) 7.4 ac test conditions note: ac test inputs are driven at v ccq for a logic "1" and 0.0 v for a logic "0." input timing begins, and output timing ends, at v ccq /2 v (50% of v ccq ). input rise and fall times (10% to 90%) < 5 ns. note: c l includes jig capacitance table 14: reset specifications # symbol parameter min max unit notes p1 t plph rp# pulse low time (if rp# is tied to v cc , this specification is not applicable) rp# is asserted during block erase, program or lock-b it configuration operation 25 ? s 1 rp# is asserted during read 100 ? ns 1 p2 t phrh rp# high to reset during block erase, program, or lock-bit configuration ? 100 ns 1,2 p3 t vccph vcc power valid to rp# de-assertion (high) 60 ? s ? notes: 1. these specifications are valid for all product versions (packages and speeds). 2. a reset time, t phqv , is required from the latter of sts (in ry/by# mode) or rp# going high until outputs are valid. figure 13: ac input/output reference waveform figure 14: transient equiva lent testing load circuit table 15: test configuration test configuration c l (pf) v ccq = v ccqmin 30 output test points input v ccq /2 v ccq 0.0 v ccq /2 device under test c l out numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 30 208032-01 8.0 bus interface this section provides an overview of bus operations. the on-chip write state machine (wsm) manages all erase and program algorithms. the system cpu provides control of all in-system read, write, and erase operations through the system bus. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. ta b l e 1 6 summarizes the necessary states of each control signal for different modes of operations. notes: 1. see ta b l e 1 7 for valid ce x configurations. 2. oe# and we# should never be asserted simultaneously. if done so, oe# overrides we#. 3. dq refers to dq[7:0] when byte# is low and dq[15:0] if byte# is high. 4. refer to dc characteristics. when v pen v penlk , memory contents can be read but not altered. 5. x should be v il or v ih for the control pins and v penlk or v penh for v pen . for outputs, x should be v ol or v oh . 6. in default mode, sts is v ol when the wsm is executing internal block erase, program, or a lock-bit configuration algorithm. it is v oh (pulled up by an exte rnal pull up resistance 10k) when the wsm is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or reset power-down mode. 7. see section 11.0, ?device command codes? on page 47 for valid din (user commands) during a write operation. 8. array writes are either program or erase operations. table 16: bus operations mode rp# ce x (1) oe# (2) we# (2) v pen dq 15:0 (3) sts (default mode) notes async., status, query and identifier reads v ih enabled v il v ih xd out high z 4,6 output disable v ih enabled v ih v ih x high z high z ? standby v ih disabledxxxhigh zhigh z? reset/power-down v il xxxxhigh zhigh z? command writes v ih enabled v ih v il xd in high z 6,7 array writes v ih enabled v ih v il v penh xv il 5,8 table 17: chip enable truth table for 32-, 64-, 128-mb ce2 ce1 ce0 device v il v il v il enabled v il v il v ih disabled v il v ih v il disabled v il v ih v ih disabled v ih v il v il enabled v ih v il v ih enabled v ih v ih v il enabled v ih v ih v ih disabled note: for single-chip applic ations, ce2 and ce1 can be connected to vss. may 2009 datasheet 208032-01 31 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) 8.1 bus reads reading from flash memory outputs stored in formation to the processor or chipset, and does not change any contents. reading can be performed an unlimited number of times. besides array data, other types of da ta such as device information and device status is available from the flash. to perform a bus read operation, cex (refer to table 17 on page 30 ) and oe# must be asserted. cex is the device-select control; when active, it enables the flash memory device. oe# is the data-output control; when active, the addressed flash memory data is driven onto the i/o bus. for all read states, we# and rp# must be de-asserted. see section 9.2, ?read operations? on page 35 . 8.1.1 asynchronous page mode read unlike backward devices, j3 65 nm sbc device provides eight-word asynchronous page mode only. array data can be sensed up to ei ght words (16 bytes) at a time. this is the default mode on power-up or reset. on backward devices, the set enhanced co nfiguration register command is used to enable eight-word page mode upon power-up or reset, however this has no effect on j3 65 nm sbc device anymore. after the initial access delay, the first word out of the page buffer corresponds to the initial address. address bits a[3:1] determ ine which word is output from the page buffer for a x16 bus width, and a[3:0] dete rmine which byte is output from the page buffer for a x8 bus width. subsequent reads from the device come from the page buffer. these reads are output on dq[15:0] for a x16 bus width and dq[7:0] for a x8 bus width after a minimum delay as long as a[3:0]. data can be read from the page buffer multip le times, and in any order.if address bits a[max:4] change at any time, or if cex# is toggled, the device will sense and load new data into the page buffer. asynchronous page mode is the default read mode on power- up or reset. to perform a page mode read after any othe r operation, the read array command must be issued to read from the flash array. asynchronous page mode reads are permitted in all blocks and are used to access register information. during register access, only one word is loaded into the page buffer. 8.1.1.1 enhanced configuration register the enhanced configuration register (ecr) is a volatile storage register that when addressed by the set ecr command can se lect between four-word page mode and eight-word page mode on backward devices, however this has no effect on j3 65 nm sbc device anymore. the ecr is volatile; all bits will be reset to default values when rp# is deasserted or power is removed from the device. to modi fy ecr settings, use the set ecr command. the set ecr command is written along with th e configuration register value, which is placed on the lower 16 bits of the addre ss bus a[15:0]. this is followed by a second write that confirms the operation and again presents the ecr data on the address bus. after executing this command, the device returns to read array mode. the ecr is shown in ta b l e 1 8 . 8-word page mode command bus-cycle is captured in ta b l e 1 9 for backward compatibility reasons. note: if the 8-word asynchronous page mode is used on j3 65 nm sbc, a clear status register command must be executed after issuing the set ecr command. numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 32 208032-01 8.1.2 output disable with cex asserted, and oe# at a logic-high level (v ih ), the device outputs are disabled. output signals dq[15:0] are placed in a high-impedance state. 8.2 bus writes writing or programming to the device, is wher e the host writes information or data into the flash device for non-volatile storage. wh en the flash device is programmed, ?ones? are changed to ?zeros?. ?zeros? cannot be programed back to ?ones?. to do so, an erase operation must be performed. writing commands to the command user interface (cui) enables various modes of operat ion, including the following: ? reading of array data ? common flash interface (cfi) data ? identifier codes, inspection, and clearing of the status register ? block erasure, program, and lock-bit configuration (when v pen = v penh ) erasing is performed on a block basis ? all flash cells within a block are erased together. any information or data previously stored in the block will be lost. erasing is typically done prior to programming. the block er ase command requires appropriate command data and an address within the block to be erased. the byte/word program command requires the command and address of the loca tion to be written. set block lock-bit commands require the command and block within the device to be locked. the clear block lock-bits command requires the command and address within the device to be cleared. the cui does not occupy an addressable memory location. it is written when the device is enabled and we# is active . the address and data needed to execute a command are latched on the rising edge of we# or ce x (ce x low is defined as the combination of pins table 18: enhanced configuration register reserved page length reserved ecr 15 ecr 14 ecr 13 ecr 12 ecr 11 ecr 10 ecr 9 ecr 8 ecr 7 ecr 6 ecr 5 ecr 4 ecr 3 ecr 2 ecr 1 ecr 0 bits description notes ecr[15:14] rfu all bits should be set to 0. ecr.13 ? ?1? = 8-word page mode for backward devices ? ?0? = 4-word page mode for backward devices ecr[12:0] rfu all bits should be set to 0. table 19: asynchronous 8-word page mode co mmand bus-cycle definition for backward devices command bus cycles required first bus cycle second bus cycle oper addr (1) data oper addr (1) data set enhanced configuration register (set ecr) 2 write ecd 0060h write ecd 0004h 1. ecd = enhanced configuration register data may 2009 datasheet 208032-01 33 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) ce0, ce1, and ce2 that enable the device. ce x high is defined as the combination of pins ce0, ce1, and ce2 that disable the device. see table 17 on page 30 ). standard microprocessor write timings are used. 8.3 standby ce0, ce1, and ce2 can disable the device (see table 17 on page 30 ) and place it in standby mode. this manipulation of cex substantially reduces device power consumption. dq[15:0] outputs are placed in a high-impedance state independent of oe#. if deselected during block erase, pr ogram, or lock-bit configuration, the wsm continues functioning, and consuming active power until the operation completes. 8.3.1 reset/power-down rp# at v il initiates the reset/power-down mode. in read modes, rp#-low deselects the memory, places output drivers in a high- impedance state, and turns off numerous internal circuits. rp# must be held low for a minimum of t plph . time t phqv is required after return from reset mode until initial memory access outputs are valid. after this wake-up interval, normal operation is restored. the cui is reset to read array mode and status register is set to 0080h. during block erase, program, or lock-bit configuration modes, rp#-low will abort the operation. in default mode, sts transitions low and remains low for a maximum time of t plph + t phrh until the reset operation is complete. memory contents being altered are no longer valid; the data may be partially corrupted after a program or partially altered after an erase or lock-bit configuration. time t phwl is required after rp# goes to logic-high (v ih ) before another command can be written. as with any automated device, it is importan t to assert rp# during system reset. when the system comes out of reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase, program, or lock-bit configuration modes. if a cpu reset occurs with no flash memory reset, proper initialization may not occur because the flash memory may be providing status information instead of array data. numonyx flash memories allow proper initialization following a system reset through the use of th e rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu. 8.4 device commands when v pen v penlk , only read operations from the status register, cfi, identifier codes, or blocks are enabled. placing v penh on v pen additionally enables block erase, program, and lock-bit configuration operat ions. device operations are selected by writing specific commands to the command user interface (cui). the cui does not occupy an addressable memory location. it is the mechanism through which the flash device is controlled. a command sequence is issued in two consecutive write cycles - a setup command followed by a confirm command. however, some commands are single-cycle commands consisting of a setup command only. generally, commands that alter the contents of the flash device, such as program or erase, require at least two write cycles to guard against inadvertent changes to the flash device. flash commands fall into two categories: basic commands and extended commands. basic commands are recognized by all numonyx flash devices, and are used to perform common flash operations such as selecting the read mode, programming the array, or erasing blocks. extended commands are product-dependant; they are used to perform additional features such as software block locking. section 11.0, ?device command codes? on page 47 describes all applicable comm ands on j3 65 nm sbc device. numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 34 208032-01 9.0 flash operations this section describes the operational features of flash memory. operations are command-based, wherein command codes are first issued to the device, then the device performs the desired operation. al l command codes are issued to the device using bus-write cycles (see chapter 8.0, ?bus interface? ). a complete list of available command codes can be found in section 11.0, ?device command codes? on page 47 . 9.1 status register the status register (sr) is an 8-bit, read-only register that indicates device status and operation errors. to read the status register, issue the read status register command. subsequent reads output status register information on dq[7:0], and 00h on dq[15:8]. sr status bits are set and cleared by the device. sr error bits are set by the device, but must be cleared using the clear status regi ster command. upon power-up or exit from reset, the status register defaults to 80h. page-mode reads are not supported in this read mode. status register contents are latched on the falling edge of oe# or ce x (ce x low is defined as the combination of pins ce0, ce1, and ce2 that enable the device. ce x high is defined as the combination of pins ce0, ce1, and ce2 that disable the device). oe# must toggle to v ih or the device must be disabled before further reads to update the status register latch. the read status register command functions independently of v pen voltage. ta b l e 2 0 shows status register bit definitions. table 20: status register bit definitions status register (sr) default value = 80h ready status erase suspend status erase error program error program/ erase voltage error program suspend status block-locked error reserved 76 5 4 3 2 1 0 bit name description 7ready status 0 = device is busy; sr[6:0] are invalid (not driven); 1 = device is ready; sr[6:0] are valid. 6 erase suspend status 0 = erase suspend not in effect. 1 = erase suspend in effect. 5 erase error command sequence error sr.5 sr.4 0 0 = program or erase operation successful. 0 1 = program error - operation aborted. 1 0 = erase error - operation aborted. 1 1 = command sequence error - command aborted. 4 program error 3 program/erase voltage error 0 = within acceptable limits du ring program or erase operation. 1 = not within acceptable limits during program or erase operation - operation aborted. 2 program suspend status 0 = program suspend not in effect. 1 = program suspend in effect. 1block-locked error 0 = block not locked during program or erase - operation successful. 1 = block locked during program or erase - operation aborted. 0 reserved reserved may 2009 datasheet 208032-01 35 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) 9.1.1 clearing the status register the status register (sr) contain status and error bits which are set by the device. sr status bits are cleared by the device, however sr error bits are cleared by issuing the clear sr command (see ta b l e 2 1 ). resetting the device also clears the sr. issuing the clear sr command places the device in read sr mode. note: care should be taken to avoid sr ambiguity. if a command sequence error occurs while in an erase suspend condition, the sr w ill indicate a command sequence error by setting sr.4 and sr.5. when the erase operation is resumed (and finishes), any errors that may have occurred during the erase operation will be masked by the command sequence error. to avoid this situation, clear the status register prior to resuming a suspended erase operation. the clear sr command functions independent of the voltage level on vpen. 9.2 read operations four types of data can be read from the device: array data, device information, cfi data, and device status. upon power-up or re turn from reset, the device defaults to read array mode. to change the device?s read mode, the appropriate command must be issued to the device. ta b l e 2 2 shows the command codes used to configure the device for the desired read mode. the follo wing sections describe each read mode. 9.2.1 read array upon power-up or return from reset, the device defaults to read array mode. issuing the read array command places the device in read array mode. subsequent reads output array data on dq[15:0]. the device remains in read array mode until a different read command is issued, or a program or erase operation is performed, in which case, the read mode is auto matically changed to read status. to change the device to read array mode while it is programming or erasing, first issue the suspend command. after the operation has been suspended, issue the read array command. when the program or erase operation is subsequently resumed, the device will automatically revert back to read status mode. note: issuing the read array command to the device while it is actively programming or erasing causes subsequent reads from the device to output invalid data. valid array data is output only after the prog ram or erase operation has finished. table 21: clear status register command bus-cycles command setup write cycle confirm write cycle address bus data bus address bus data bus clear status register device address 0050h ? ? table 22: read mode command bus-cycles command setup write cycle confirm write cycle address bus data bus address bus data bus read array device address 00ffh ? ? read status register device address 0070h ? ? read device information device address 0090h ? ? cfi query device address 0098h ? ? numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 36 208032-01 the read array command functions indepe ndent of the voltage level on vpen. 9.2.2 read status register issuing the read status register command places the device in read status register mode. subsequent reads output status regi ster information on dq[7:0], and 00h on dq[15:8]. the device remains in read status register mode until a different read- mode command is issued. performing a program, erase, or block-lock operation also changes the device?s read mode to read status register mode. the status register is updated on the falling edge of oe# or cex, whichever occurs last. status register contents are valid only when sr.7 = 1. when wsm is active, sr.7 indicates the wsm?s state and sr[6:0] are in high-z state. the read status register command functions independent of the voltage level on vpen. 9.2.3 read device information issuing the read device information command places the device in read device information mode. subsequent reads output device information on dq[15:0]. the device remains in read device informat ion mode until a different read command is issued. also, performing a program, erase, or block-lock operation changes the device to read status register mode. the read device information command functi ons independent of the voltage level on vpen. 9.2.4 cfi query the cfi query table contains an assortment of flash product information such as block size, density, allowable command sets, electrical specifications, and other product information. the data contained in this table conforms to the cfi protocol. issuing the cfi query command places the device in cfi query mode. subsequent reads output cfi information on dq[15:0]. the device remains in cfi query mode until a different read command is issued, or a program or erase operation is performed, which changes the read mode to read status register mode. the cfi query command functions independent of the voltage level on vpen. 9.3 programming operations all programming operations require the addressed block to be unlocked, and a valid vpen voltage applied throughout the programming operation. otherwise, the programming operation will abor t, setting the appropriate status register error bit(s). the following sections describe each programming method. 9.3.1 single-word/byte programming array programming is performed by firs t issuing the single-word/byte program command. this is followed by writing the desi red data at the desired array address. the read mode of the device is automatically changed to read status register mode, which remains in effect until another read-mode command is issued. may 2009 datasheet 208032-01 37 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) during programming, sts and the status register indicate a busy status (sr.7 = 0). upon completion, sts and the status register indicate a ready status (sr.7 = 1). the status register should be checked for any errors (sr.4), then cleared. note: issuing the read array command to the device while it is actively programming causes subsequent reads from the device to output in valid data. valid array data is output only after the program operation has finished. standby power levels are not be realized un til the programming operation has finished. also, asserting rp# aborts the programming operation, and array contents at the addressed location are indeterminate. the addressed block should be erased, and the data re-programmed. if a single-word/ byte program is attempted when the corresponding block lock-bit is set, sr.1 and sr.4 will be set. 9.3.2 buffered programming buffered programming operations simultaneo usly program multiple words/bytes into the flash memory array, significantly reduci ng effective word-write/byte-write times. user-data is first written to a write buff er, then programmed into the flash memory array in buffer-size increments. for additi onal details, see the flow chart of the buffered-programming operation. note: optimal performance and power consumption is realized by aligning the start address on 256-word boundaries (i.e., a[8:0] = 000000000b). crossing a 256-word boundary during a buffered programming operation can cause programming time to double. to perform a buffered programming operatio n, first issue the buffered program setup command at the desired starting address. the read mode of the device/addressed partition is automatically changed to read status register mode. polling sr.7 determines write-buffer availability (0 = not available, 1 = available). if the write buffer is not available, re-issue the setup command and check sr.7; repeat until sr.7 = 1. next, issue the word count at the desired starting address. the word count represents the total number of words to be written into the write buffer, minus one. this value can range from 00h (one) to a maximum of ffh (256). exceeding the allowable range causes an abort. note: the maximum number of bytes in write buffer on cfi region (offset 2ah, refer table 41, ?device geometry definition? on page 60 ) is set to 05h (32 bytes) for backward compatible reasons. no software change is re quired on existing applications for both x8 and x16 mode. applications can optimize the system performance using the maximum of 256 buffer size, contact your sales representives for questions. following the word count, the write buffer is filled with user-data. subsequent bus- write cycles provide addresses and data, up to the word count. all user-data addresses must lie between numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 38 208032-01 array programming.issuing the read array comma nd to the device while it is actively programming or erasing causes subsequent reads from the device to output invalid data. valid array data is output only after the program or erase operation has finished. upon completion of array programming, the status register indicates ready (sr.7 = 1). a full status register check should be performed to check for any programming errors, then cleared by using the clear status register command. additional buffered programming operations can be initiated by issuing another setup command, and repeating the buffered progra mming bus-cycle sequence. however, any errors in the status register must fi rst be cleared before another buffered programming operation can be initiated. 9.4 block erase operations erasing a block changes ?zeros? to ?ones?. to change ones to zeros, a program operation must be performed (see section 9.3, ?programming operations? ). erasing is performed on a block basis - an entire block is erased each time an erase command sequence is issued. once a block is fully erased, all addressable locations within that block read as logical ones (ffffh for x16 mode, ffh for x8 mode). only one block-erase operation can occur at a time, and is not permitted during a program suspend. to perform a block-erase operation, issue the block erase command sequence at the desired block address. ta b l e 2 3 shows the two-cycle block erase command sequence. note: a block-erase operation requires the addressed block to be unlocked, and a valid voltage applied to vpen throughout the block-erase operation. otherwise, the operation will abort, setting the appropriate status register error bit(s). the erase confirm command latches the ad dress of the block to be erased. the addressed block is preconditioned (programmed to all zeros), erased, and then verified. the read mode of the device is automatica lly changed to read status register mode, and remains in effect until another read-mode command is issued. during a block-erase operation, sts and the status register indicates a busy status (sr.7 = 0). upon completion, sts and the st atus register indicates a ready status (sr7 = 1). the status register should be checked for any errors, then cleared. if any errors did occur, subsequent erase commands to the device are ignored unless the status register is cleared. the only valid commands during a block eras e operation are read array, read device information, cfi query, and erase suspend. after the block-erase operation has completed, any valid command can be issued. note: issuing the read array command to the device while it is actively erasing causes subsequent reads from the device to output invalid data. valid array data is output only after the block-erase operation has finished. standby power levels are not be realized until the block-erase operation has finished. also, asserting rp# aborts the block-erase operation, and array contents at the addressed location are indeterminate. the addressed block should be erased before programming within the block is attempted. table 23: block-erase command bus-cycles command setup write cycle confirm write cycle address bus data bus address bus data bus block erase device address 0020h block address 00d0h may 2009 datasheet 208032-01 39 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) 9.5 suspend and resume an erase or programming operation can be suspended to perform other operations, and then subsequently resumed. ta b l e 2 4 shows the suspend and resume command bus- cycles. note: all erase and programming operations require the addressed block to remain unlocked with a valid voltage applied to vpen throug hout the suspend operation. otherwise, the block-erase or programming operation will abort, setting the appropriate status register error bit(s). also, asserting rp# aborts suspended block-erase and programming operations, rendering array contents at the addressed location(s) indeterminate. to suspend an on-going erase or program operation, issue the suspend command to any device address. the program or erase op eration suspends at pre-determined points during the operation after a delay of t susp . suspend is achieved whensts (in ry/by# mode) goes high, sr[7,6] = 1 (erase-suspend) or sr[7,2] = 1 (program-suspend). note: issuing the suspend command does not change the read mode of the device. the device will be in read status register mode from when the erase or program command was first issued, unless the read mode was changed prior to issuing the suspend command. not all commands are allowed when the device is suspended. ta b l e 2 5 shows which device commands are allowed during program suspend or erase suspend. table 24: suspend and resume command bus-cycles command setup write cycle confirm write cycle address bus data bus address bus data bus suspend device address 00b0h ? ? resume device address 00d0h ? ? table 25: valid commands during suspend device command program suspend erase suspend sts configuration allowed allowed read array allowed allowed read status register allowed allowed clear status register allowed allowed read device information allowed allowed cfi query allowed allowed word/byte program not allowed allowed buffered program not allowed allowed block erase not allowed not allowed program suspend not allowed allowed erase suspend not allowed not allowed program/erase resume allowed allowed lock block not allowed not allowed unlock block not allowed not allowed program otp register not allowed not allowed numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 40 208032-01 during suspend, array-read operations ar e not allowed in blocks being erased or programmed. a block-erase under program-suspend is not allowed. however, word-program under erase-suspend is allowed, and can be suspended. this results in a simultaneous erase- suspend/ program-suspend condition, indicated by sr[7,6,2] = 1. to resume a suspended program or erase operation, issue the resume command to any device address. th e read mode of the device is automatically changed to read status register. the operation continues where it left off, sts (in ry/by# mode) goes low, and the respective status register bits are cleared. when the resume command is issued during a simultaneous erase-suspend/ program- suspend condition, the programming operation is resumed first. upon completion of the programming operation, the status register should be checked for any errors, and cleared. the resume command must be issued again to complete the erase operation. upon completion of the erase operation, the status register should be checked for any errors, and cleared. 9.6 status signal the status (sts) signal can be configur ed to different states using the sts configuration command ( ta b l e 2 6 ). once the sts signal has been configured, it remains in that configuration until another configuration command is issued or rp# is asserted low. initially, the sts signal defa ults to ry/by# operation where ry/by# low indicates that the wsm is busy. ry/by# high indicates that the state machine is ready for a new operation or suspended. ta b l e 2 7 displays possible sts configurations. to reconfigure the status (sts) signal to other modes, the configuration command is given followed by the desired configuration co de. the three alternate configurations are all pulse mode for use as a system interrupt as described in the following paragraphs. for these configurations, bit 0 controls erase complete interrupt pulse, and bit 1 controls program complete interrupt pulse. supplying the 00h configuration code with the configuration command resets the sts signal to the default ry/by# level mode. the configuration command may only be given when the device is not busy or suspended. check sr.7 for device status. an invalid configuration code will result in sr.4 and sr.5 being set. note: sts pulse mode is not supported in the clear lock bits and set lock bit commands. table 26: sts configuration register command bus-cycles command setup write cycle confirm write cycle address bus data bus address bus data bus sts configuration device address 00b8h device address register data may 2009 datasheet 208032-01 41 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) 9.7 security and protection j3 65 nm sbc device offers both hardware and software security features. block lock operations, prs and vpen allow users to implement various levels of data protection. 9.7.1 normal block locking j3 65 nm sbc has the capability of flexible block locking (locked blocks remain locked upon reset or power cycle): all blocks within the device are in unlocked state when ship from numonyx. blocks can be locked individually by issuing the set block lock bit command sequence to any address within a block. once locked, blocks remain locked when power is removed, or when the device is reset. all locked blocks are unlocked simultaneously by issuing the clear block lock bits command sequence to any device address. locked blocks cannot be erased or programmed. ta b l e 2 8 summarizes the command bus-cycles. after issuing the set block lock bit setup command or clear block lock bits setup command, the device?s read mode is automa tically changed to read status register mode. after issuing the confirm command, comp letion of the operation is indicated by sts (in ry/by# mode) going high and sr.7 = 1. blocks cannot be locked or unlocked while programming or erasing, or while the device is suspended. reliable block lock and unlock operations occur only when v cc and v pen are valid. when v pen v penlk , block lock-bits cannot be changed. table 27: sts configuration regi ster and coding definitions d7 d6 d5 d4 d3 d2 d1 d0 reserved 3 pulse on program complete 1 pulse on erase complete 1 d[1:0] = sts configuration codes 2 notes 00 = default, level mode; device ready indication controls hold to a memory controller to prevent accessing a flash memory subsystem while any flash device's wsm is busy. 01 = pulse on erase complete generates a system interrupt pulse when any flash device in an array has completed a block erase. helpful for reform atting blocks after file system free space reclamation or ?cleanup.? 10 = pulse on program complete no t supported on this device. 11 = pulse on erase or program complete generates system interrupts to trigger se rvicing of flash arrays when either erase or program operations are completed, when a common interrupt service routine is desired. notes: 1. when configured in one of the pulse modes, sts pulses low with a typical pulse width of 500 ns. 2. an invalid configuration code will result in both sr.4 and sr.5 being set. 3. reserved bits are invalid should be ignored. table 28: block locking command bus-cycles command setup write cycle confirm write cycle address bus data bus address bus data bus set block lock bit block ad dress 0060h block address 0001h clear block lock bits device address 0060h device address 00d0h numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 42 208032-01 when the set lock-bit operation is complete , sr.4 should be checked for any error. when the clear lock-bit operation is comple te, sr.5 should be checked for any error. errors bits must be cleared using the clear status register command. block lock-bit status can be determined by first issuing the read device information command, and then reading from may 2009 datasheet 208032-01 43 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) outside the defined pr address space will result in a status register error (sr.4 will be set). attempting to program a locked pr segment will result in a status register error (sr.4 and sr.1 will be set). 9.7.7 locking the 128-bit protection register the user-programmable segment of the pr is lockable by programming bit 1 of the protection lock register (plr) to 0. bit 0 of this location is programmed to 0 at the numonyx factory to protect the unique device number. bit 1 is set using the protection program command to program ?0xfffd? to the plr. after these bits have been programmed, no further changes can be made to the values stored in the protection register. protection program commands to a locked section will result in a status register error (sr.4 and sr.1 will be set). the pr lockout state is not reversible. note: a0 is not used in x16 mode when accessing the protection register map. see ta b l e 3 1 for x16 addressing. in x8 mode a0 is used, see ta b l e 3 2 for x8 addressing. table 29: programming the 128-bit prot ection register command bus-cycles command first bus cycle second bus cycle address bus data bus address bus data bus program otp register device address 00c0h register offset register data table 30: programming protection lock register command bus-cycles command first bus cycle second bus cycle address bus data bus address bus data bus program otp register device address 00c0h 80h fffdh figure 15: 128-bit protecti on register memory map 0x 88 0x 85 64- bit segment ( user- pr ogrammable ) 0x 84 0x 81 0x 80 protection lock register 64- bit segment (factory - pr ogrammed ) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 128-bit protection register 0x 82 0x 83 0x 86 0x 87 word address 128-mbit: a[23:1] 64-mbit: a[22:1] 32-mbit: a[21:1] numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 44 208032-01 9.7.8 vpen protection when it?s necessary to protect the entire arra y, global protection can be achieved using a hardware mechanism using vpp or vpen. whenever a valid voltage is present on vpp or vpen, blocks within the main flash array can be erased or programmed. by grounding vpp or vpen, blocks within the main array cannot be altered ? attempts to table 31: word-wide protec tion register addressing word use a8a7a6a5a4a3a2a1 lock both 10000000 0 factory 10000001 1 factory 10000010 2 factory 10000011 3 factory 10000100 4 user 10000101 5 user 10000110 6 user 10000111 7 user 10001000 note: all address lines not specified in the above table must be 0 when accessing the protection register (i.e., a[max:9] = 0.) table 32: byte-wide protection register addressing byteusea8a7a6a5a4a3a2a1a0 lockboth100000000 lockboth100000001 0factory100000010 1factory100000011 2factory100000100 3factory100000101 4factory100000110 5factory100000111 6factory100001000 7factory100001001 8user100001010 9user100001011 auser100001100 buser100001101 cuser100001110 duser100001111 euser100010000 fuser100010001 note: all address lines not specified in the above table must be 0 when accessing the protection register, i.e., a[max:9] = 0. may 2009 datasheet 208032-01 45 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) program or erase blocks will fail resulting in the setting of the appropriate error bit in the status register. by holding vpp or vpen low, absolute write protection of all blocks in the array can be achieved. numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 46 208032-01 10.0 id codes table 33: read identifier codes code address data device code 32-mbit 00001h 0016h 64-mbit 00001h 0017h 128-mbit 00001h 0018h may 2009 datasheet 208032-01 47 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) 11.0 device command codes for a complete definition on device operations refer to section 8.4, ?device commands? on page 33 . the list of all applicable commands are included here one more time for the convenience. table 34: command bus cycles and command codes command setup write cycle confirm write cycle address bus data bus address bus data bus registers program enhanced configuration register register data 0060h register data 0004h program otp register device address 00c0h register offset register data clear status register device address 0050h ? ? program sts configuration register device address 00b8h device address register data read modes read array device address 00ffh ? ? read status register device address 0070h ? ? read identifier codes (read device information) device address 0090h ? ? cfi query device address 0098h ? ? program and erase word/byte program device address 0040h/ 0010h device address array data buffered program device addr ess 00e8h device address 00d0h block erase block address 0020h block address 00d0h program/erase suspend device address 00b0h ? ? program/erase resume device address 00d0h ? ? security set block lock bit block address 0060h block address 0001h clear block lock bits device ad dress 0060h device address 00d0h numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 48 208032-01 12.0 flow charts figure 16: write to buffer flowchart start setup -write 0xe8 - block address check buffer status - perform read operation - read ready status on signal sr.7 sr.7 = 1 ? word count - address = block address - data = word count minus 1 (valid range = 0x00 to 0xff) load buffer - fill write buffer up to word c ount - address = within buffer range - data = user data confirm - write 0xd0 - block address read status register (sr) sr.7 = 1 ? full status register check (if desired) end no no yes yes may 2009 datasheet 208032-01 49 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) figure 17: status register flowchart start sr7 = '1' sr2 = '1' sr4 = '1' sr3 = '1' sr1 = '1' yes yes yes no no no no sr6 = '1' yes no sr5 = '1' no no error command sequence yes yes yes error erase failure error program failure - set by wsm - reset by user - see clear status register command - set/reset by wsm sr4 = '1' yes no end command cycle - issue status register command - address = any dev ice address - data = 0x70 erase suspend see suspend/resume flowchart program suspend see suspend/resume flowchart error v pen < v penlk error block locked data cycle - read status register sr[7:0] numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 50 208032-01 figure 18: byte/word program flowchart start write 40h, address write data and address read status register sr.7 = full status check if desired byte/word program complete read status register data (see above) voltage range error device protect error programming error byte/word program successful sr.3 = sr.1 = sr.4 = full status check procedure bus operation write write standby 1. toggling oe# (low to high to low) updates the status register. this can be done in place of issuing the read status register command. repeat for subsequent programming operations. sr full status check can be done after each program operation, or after a sequence of programming operations. write ffh after the last program operation to place device in read array mode. bus operation standby standby toggling oe# (low to high to low) updates the status register. this can be done in place of issuing the read status register command. repeat for subsequent programming operations. sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are programmed before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. 0 1 1 0 1 0 1 0 command setup byte/ word program byte/word program comments data = 40h addr = location to be programmed data = data to be programmed addr = location to be programmed check sr.7 1 = wsm ready 0 = wsm busy command comments check sr.3 1 = programming to voltage error detect check sr.4 1 = programming error read (note 1) status register data standby check sr.1 1 = device protect detect rp# = v ih , block lock-bit is set only required for systems implemeting lock-bit configuration. may 2009 datasheet 208032-01 51 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) figure 19: program suspend/resume flowchart start write b0h read status register sr.7 = sr.2 = programming completed write d0h programming resumed write ffh read array data 1 1 0 0 bus operation command comments write program suspend data = b0h addr = x read status register data addr = x standby check sr.7 1 - wsm ready 0 = wsm busy standby check sr.6 1 = programming suspended 0 = programming completed read read array locations other than that being programmed. write ffh read data array done reading yes no write read array data = ffh addr = x write program resume data = d0h addr = x numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 52 208032-01 figure 20: block erase flowchart start read status register sr.7 = erase flash block(s) complete 0 1 full status check if desired suspend erase issue single block erase command 20h, block address suspend erase loop write confirm d0h block address yes no bus operation command comments write erase block data = 20h addr = block address write (note 1) erase confirm data = d0h addr = block address read status register data with the device enabled, oe# low updates sr addr = x standby check sr.7 1 = wsm ready 0 = wsm busy 1. the erase confirm byte must follow erase setup. this device does not support erase queuing. please see application note ap-646 for software erase queuing compatibility. full status check can be done after all erase and write sequences complete. write ffh after the last operation to reset the device to read array mode. may 2009 datasheet 208032-01 53 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) figure 21: block erase suspend/resume flowchart start write b0h read status register sr.7 = sr.6 = block erase completed read or program? done? write d0h block erase resumed write ffh read array data program program loop read array data read no yes 1 1 0 0 bus operation command comments write erase suspend data = b0h addr = x read status register data addr = x standby check sr.7 1 - wsm ready 0 = wsm busy standby check sr.6 1 = block erase suspended 0 = block erase completed write erase resume data = d0h addr = x numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 54 208032-01 figure 22: set block lock-bit flowchart start write 60h, block address write 01h, block address read status register sr.7 = full status check if desired set lock-bit complete full status check procedure bus operation write 1 0 command set block lock-bit setup comments data = 60h addr =block address read status register data (see above) voltage range error sr.3 = 1 0 command sequence error sr.4,5 = 1 0 set lock-bit error sr.4 = 1 0 set lock-bit successful bus operation standby command comments check sr.3 1 = programming voltage error detect sr.5, sr.4 and sr.3 are only cleared by the clear status register command, in cases where multiple lock-bits are set before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. standby check sr.4, 5 both 1 = command sequence error standby check sr.4 1 = set lock-bit error write set block lock-bit confirm data = 01h addr = block address standby repeat for subsequent lock-bit operations. full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. write ffh after the last lock-bit set operation to place device in read array mode. check sr.7 1 = wsm ready 0 = wsm busy read status register data may 2009 datasheet 208032-01 55 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) figure 23: clear lock-bit flowchart start write 60h write d0h read status register sr.7 = full status check if desired clear block lock-bits complete full status check procedure bus operation write write standby write ffh after the clear lock-bits operation to place device in read array mode. bus operation standby sr.5, sr.4, and sr.3 are only cleared by the clear status register command. if an error is detected, clear the status register before attempting retry or other error recovery. 1 0 command clear block lock-bits setup clear block or lock-bits confirm comments data = 60h addr = x data = d0h addr = x check sr.7 1 = wsm ready 0 = wsm busy command comments check sr.3 1 = programming voltage error detect read status register data (see above) voltage range error sr.3 = 1 0 command sequence error sr.4,5 = 1 0 clear block lock-bits error sr.5 = 1 0 read status register data standby check sr.4, 5 both 1 = command sequence error standby check sr.5 1 = clear block lock-bits error clear block lock-bits successful numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 56 208032-01 figure 24: protection register programming flowchart start write c0h (protection reg. program setup) write protect. register address/data read status register sr.7 = 1? full status check if desired program complete read status register data (see above) v pen range error protection register programming error attempted program to locked register - aborted program successful sr.3, sr.4 = sr.1, sr.4 = sr.1, sr.4 = full status check procedure bus operation write write standby protection program operations can only be addressed within the protection register address space. addresses outside the defined space will return an error. repeat for subsequent programming operations. sr full status check can be done after each program or after a sequence of program operations. write ffh after the last program operation to reset device to read array mode. bus operation standby standby sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.1, sr.3 and sr.4 are only cleared by the clear staus register command, in cases of multiple protection register program operations before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes 1, 1 0,1 1,1 command protection program setup protection program comments data = c0h data = data to program addr = location to program check sr.7 1 = wsm ready 0 = wsm busy command comments sr.1 sr.3 sr.4 0 1 1 v pen low 0 0 1 prot. reg. prog. error 1 0 1 register locked: aborted read status register data toggle ce# or oe# to update status register data standby may 2009 datasheet 208032-01 57 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) 13.0 common flash interface the (cfi) specification outlines device and host system software interrogation handshake which allows specific vendor-speci fied software algorithms to be used for entire families of devices. this allows de vice independent, jede c id-independent, and forward- and backward-compatible software support for the specified flash device families. it allows flash vendors to standard ize their existing interfaces for long-term compatibility. this section defines the data structure or ?database? returned by the (cfi) query command. system software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. once this information has been obtained, the software will know whic h command sets to use to enable flash writes, block erases, and otherwise control the flash component. the query is part of an overall specification for multiple command set and control interface descriptions called cfi. 13.1 query structure output the query ?database? allows system software to gain information for controlling the flash component. this section describes the de vice?s cfi-compliant interface that allows the host system to access query data. query data are always presented on the lowest-order data outputs (d[7:0]) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the query table device starting address is a 10h, which is a word address for x16 devices. for a word-wide (x16) device, the first two by tes of the query structure, ?q? and ?r? in ascii, appear on the low byte at word addresses 10h and 11h. this cfi-compliant device outputs 00h data on upper bytes. t hus, the device outputs ascii ?q? in the low byte (d[7:0]) and 00h in the high byte (d[15:8]). at query addresses containing two or more bytes of information, the least significant data byte is presented at the lower addre ss, and the most significant data byte is presented at the higher address. in all of the following tables, addresses and data are represented in hexadecimal notation, so the ?h? suffix has been dropped. in addition, since the upper byte of word- wide devices is always ?00h,? the leadin g ?00? has been dropped from the table notation and only the lower byte value is shown. any x16 device outputs can be assumed to have 00h on the upper byte in this mode. table 35: summary of query structure outp ut as a function of device and mode device type/ mode query start location in maximum device bus width addresses query data with maximum device bus width addressing query data with byte addressing hex offset hex code ascii value hex offset hex code ascii value x16 device 10h 10: 0051 ?q? 20: 51 ?q? x16 mode 11: 0052 ?r? 21: 00 ?null? 12: 0059 ?y? 22: 52 ?r? x16 device 20: 51 ?q? numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 58 208032-01 13.2 query structure overview the query command causes the flash co mponent to display the common flash interface (cfi) query structure or ?databas e.? the structure sub-sections and address locations are summarized below. see ap-646 common flash interface (cfi) and command sets (order number 292204) for a full description of cfi. the following sections describe the query structure sub-sections in detail. x8 mode n/a (1) n/a (1) 21: 51 ?q? 22: 52 ?r? note: 1. the system must drive the lowest order addresses to access all the device's array data when the device is configured in x8 mode. therefore, word addressing, where these lower addresses are not toggled by the system, is "not applicable" for x8-configured devices. table 36: example of query structure ou tput of a x16- and x8-capable device word addressing byte addressing offset hex code value offset hex code value a 15 ?a 0 d15?d 0 a 7 ?a 0 d 7 ?d 0 0010h 0051 ?q? 20h 51 ?q? 0011h 0052 ?r? 21h 51 ?q? 0012h 0059 ?y? 22h 52 ?r? 0013h p_id lo prvendor 23h 52 ?r? 0014h p_id hi id # 24h 59 ?y? 0015h p lo prvendor 25h 59 ?y? 0016h p hi tbladr 26h p_id lo prvendor 0017h a_id lo altvendor 27h p_id lo prvendor 0018h a_id hi id # 28h p_id hi id # ... ... ... ... ... ... table 35: summary of query structure outp ut as a function of device and mode device type/ mode query start location in maximum device bus width addresses query data with maximum device bus width addressing query data with byte addressing hex offset hex code ascii value hex offset hex code ascii value table 37: query structure offset sub-section name description notes 00h identification code manufacturer code 1 01h identification code device code 1 (ba+2)h (2) block status register block-specific information 1,2 04-0fh reserved reserved for vendor-specific information 1 10h cfi query identification string reserved for vendor-specific information 1 1bh system interface information command set id and vendor data offset 1 may 2009 datasheet 208032-01 59 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) 13.3 block status register the block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. 13.4 cfi query identification string the cfi query identification string provides verification that the component supports the common flash interface specification. it also indicates the specification version and supported vendor-specified command set(s). 27h device geometry definition flash device layout 1 p (3) primary numonyx-specific extended query table vendor-defined additional information specific to the primary vendor algorithm 1,3 notes: 1. refer to the query structure output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. ba = block address beginning location (i.e., 02000h is block 2?s beginning location when the block size is 128 kb). 3. offset 15 defines ?p? which points to the primary numonyx-specific extended query ta b l e . table 37: query structure offset sub-section name description notes table 38: block status register offset length description address value (ba+2)h (1) 1 block lock status register ba+2: --00 or --01 bsr.0 block lock status 0 = unlocked 1 = locked ba+2: (bit 0): 0 or 1 bsr 1?15: reserved for future use ba+2: (bit 1?15): 0 note: 1. ba = the beginning location of a bloc k address (i.e., 010000h is block 1?s (64- kw block) beginning location in word mode). table 39: cfi identification offset length description add. hex code value 10h 3 query-unique ascii string ?qry? 10 --51 ?q? 11: --52 ?r? 12: --59 ?y? 13h 2 primary vendor command set and control interface id code. 13: --01 16-bit id code for vendor-specified algorithms 14: --00 15h 2 extended query table primary algorithm address 15: --31 16: --00 17h 2 alternate vendor command set an d control interface id code. 17: --00 0000h means no second vendor-specified algorithm exists 18: --00 19h 2 secondary algorithm extended query table address. 19: --00 0000h means none exists 1a: --00 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 60 208032-01 13.5 system interface information the following device information can optimize system interface software. 13.6 device geometry definition this field provides critical details of the flash device geometry. table 40: system interface information offset length description add. hex code value 1bh 1 v cc logic supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts 1b: --27 2.7 v 1ch 1 v cc logic supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts 1c: --36 3.6 v 1dh 1 v pp [programming] supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts 1d: --00 0.0 v 1eh 1 v pp [programming] supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts 1e: --00 0.0 v 1fh 1 ?n? such that typical single word program time-out = 2 n s 1f: --06 64 s 20h 1 ?n? such that typical max. buffer write time-out = 2 n s 20: --07 1 128 s 1 21h 1 ?n? such that typical block erase time-out = 2 n ms 21: --0a 1 s 22h 1 ?n? such that typical full chip erase time-out = 2 n ms 22: --00 na 23h 1 ?n? such that maximum word program time-out = 2 n times typical 23: --02 256 s 24h 1 ?n? such that maximum buffer write time-out = 2 n times typical 24: --03 2048s 25h 1 ?n? such that maximum block erase time-out = 2 n times typical 25: --02 4 s 26h 1 ?n? such that maximum chip erase time-out = 2 n times typical 26: --00 na notes: 1. the value is 32 bytes buffer write typical time out table 41: device geometry definition (sheet 1 of 2) offset length description code see table below 27h 1 ?n? such that device size = 2 n in number of bytes 27: 28h 2 flash device interface: x8 async x16 async x8/x16 async 28: --02 x8/ x16 28:00,29:00 28:01,29:00 28:02,29:00 29: --00 2ah 2 ?n? such that maximum number of bytes in write buffer = 2 n 2a: --05 1 32 1 2b: --00 2ch 1 number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in ?bulk? 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks 3. symmetrically blocked partitions have one blocking region 4. partition size = (total blocks) x (individual block size) 2c: --01 1 may 2009 datasheet 208032-01 61 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) 13.7 primary-vendor specific extended query table certain flash features and commands are optional. the primary vendor-specific extended query table specifies this and other similar information. 2dh 4 erase block region 1 information 2d: bits 0?15 = y, y+1 = number of identical-size erase blocks 2e: bits 16?31 = z, region erase block(s) size are z x 256 bytes 2f: 30: notes: 1. compatible with j3 130nm device (32 bytes). j3 65 nm sbc device supports up to maximum 256 words (x16 mode)/ 256 bytes (x8 mode) buffer write. table 42: device geometry: address codes address 32 mbit 64 mbit 128 mbit 27: --16 --17 --18 28: --02 --02 --02 29: --00 --00 --00 2a: --05 --05 --05 2b: --00 --00 --00 2c: --01 --01 --01 2d: --1f --3f --7f 2e: --00 --00 --00 2f: --00 --00 --00 30: --02 --02 --02 table 41: device geometry definition (sheet 2 of 2) offset length description code see table below table 43: primary vendor-specific extended query (sheet 1 of 2) offset (1) p = 31h length description (optional flash features and commands) add. hex code value (p+0)h 3 primary extended query table 31: --50 ?p? (p+1)h unique ascii string ?pri? 32: --52 ?r? (p+2)h 33: --49 ?i? (p+3)h 1 major version number, ascii 34: --31 ?1? (p+4)h 1 minor version number, ascii 35: --31 ?1? numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 62 208032-01 (p+5)h (p+6)h (p+7)h (p+8)h 4 optional feature and command support (1=yes, 0=no) undefined bits are ?0.? if bit 31 is ?1? then another 31 bit field of optional features follows at the end of the bit-30 field. 36: --ce 37: --00 38: --00 39: --00 bit 0 chip erase supported bit 0 = 0 no bit 1 suspend erase supported bit 1 = 1 yes bit 2 suspend program supported bit 2 = 1 yes bit 3 legacy lock/unlock supported bit 3 = 1 (1) yes (1) bit 4 queued erase supported bit 4 = 0 no bit 5 instant individual block locking supported bit 5 = 0 no bit 6 protection bits supported bit 6 = 1 yes bit 7 page-mode read supported bit 7 = 1 yes bit 8 synchronous read supported bit 8 = 0 no bit9 simultaneous operat ion supported bit 9 = 0 no bit 30 cfi link(s) to follow (32, 64, 128 mb) bit 30 = 0 no bit 31 another ?optional feature? field to follow bit 31 = 0 no (p+9)h 1 supported functions after suspend: read array, status, query other supported operations are: bits 1?7 reserved; undefined bits are ?0? 3a: --01 bit 0 program supported after erase suspend bit 0 = 1 yes (p+a)h (p+b)h 2 block status register mask 3b: --01 bits 2?15 are reserved; undefined bits are ?0? 3c: --00 bit 0 block lock-bit status register active bit 0 = 1 yes bit 1 block lock-down bit status active bit 1 = 0 no (p+c)h 1 v cc logic supply highest performance program/erase voltage bits 0?3 bcd value in 100 mv bits 4?7 bcd value in volts 3d: --33 3.3 v (p+d)h 1 v pp optimum program/erase supply voltage bits 0?3 bcd value in 100 mv bits 4?7 hex value in volts 3e: --00 0.0 v note: 1. future devices may not support the described ?legacy lock/unlock? function. thus bit 3 would have a value of ?0.? 2. setting this bit, will lead to the extension of the cfi table. table 43: primary vendor-specific extended query (sheet 2 of 2) offset (1) p = 31h length description (optional flash features and commands) add. hex code value may 2009 datasheet 208032-01 63 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) table 44: protection register information offset (1) p = 31h length description (optional flash features and commands) add. hex code value (p+e)h 1 number of protection register fields in jedec id space. ?00h,? indicates that 256 protection bytes are available 3f: --01 01 (p+f)h (p+10)h (p+11)h (p+12)h 4 protection field 1: protection description this field describes user-available one time programmable (otp) protection register bytes. some are pre-programmed with device- unique serial numbers. others are user-programmable. bits 0-15 point to the protection register lock byte, the section?s first byte. the following bytes are factory pre-programmed and user-programmable. bits 0-7 = lock/bytes jedec-plane physical low address bits 8-15 = lock/bytes jedec-plane physical high address bits 16-23 = ?n? such that 2 n = factory pre-programmed bytes bits 24-31 = ?n? such that 2 n = user-programmable bytes 40: 41: 42: 43: --80 --00 --03 --03 80h 00h 8bytes 8bytes note: 1. the variable p is a pointer whic h is defined at cfi offset 15h. table 45: burst read information offset (1) p = 31h length description (optional flash features and commands) add. hex code value (p+13)h 1 page mode read capability bits 0?7 = ?n? such that 2 n hex value represents the number of read- page bytes. see offset 28h for devi ce word width to determine page- mode data output width. 00h indicates no read page buffer. 44: --04 16 byte (p+14)h 1 number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. 45: --00 0 (p+15)h 1 synchronous mode read capability configuration 1 bits 3-7 = reserved bits 0-2 = ?n? such that 2 n+1 hex value represents the maximum number of continuous synchronous burst reads when the device is configured for its maximum word widt h. a value of 07h indicates that the device is capable of continuous linear bursts until that will output data until the internal burst counte r reaches the end of the device?s burstable address space. this field?s 3-bit value can be written directly to the read configuration register bits 0-2 if the device is configured for its maximum word width. see offset 1fh for word width to determine the burst data output width. 46: --00 n/a (p+16h)h 1 synchronous mode read capability configuration 2 47: --00 n/a (p+45h)h 1 j3c mark for vil fix for customers 76: --01 01 note: 1. the variable p is a pointer whic h is defined at cfi offset 15h. numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 64 208032-01 appendix a additional information order number document/tool 316577 numonyx? embedded flash memory (j3 v d); 28f256j3d, 28f128j3d, 28f640j3d, 28f320j3d specification update 298136 numonyx? persistent storage manage r (psm) user?s guide software manual 292204 ap-646 common flash interface (cfi) and command sets note: contact your local numonyx or distribution sales office or visit the numonyx home page http://www.numonyx.com for technical documentation, tools, or the most current in formation on numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) . may 2009 datasheet 208032-01 65 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) appendix b ordering information figure 25: decoder for 32-, 64-, 128-mbit l pc28f320j3f75 package te = 56-lead tsop js = pb-free 56-tsop rc = 64- ball eas y bga pc = 64-ball pb-free easy bga product line designator device density 128 = x8/x16 (128-mbit ) 640 = x8/x16 ( 64-mbit ) 320 = x8/x16 ( 32-mbit ) acce ss s pe e d 75ns f = numonyx tm 0.065 micron lithography voltage (v cc /v pen) 3 = 3 v/3 v product family j = numonyx tm embedded flash memory table 46: valid combinations 32-mbit 64-mbit 128-mbit te28f320j3f75 te28f640j3f75 te28f128j3f75 js28f320j3f75 js28f640j3f75 js28f128j3f75 rc28f320j3f75 rc28f640j3f75 rc28f128j3f75 pc28f320j3f75 pc28f640j3f75 pc28f128j3f75 numonyx? embedded flash memory (j3 65 nm) single bit per cell (sbc) datasheet may 2009 66 208032-01 |
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